The present invention relates to a non-volatile semiconductor memory device and a semiconductor disk device. Specifically, the invention relates to the technique useful for non-volatile memory devices capable of having their pieces of stored information erased electrically at once (it will be called xe2x80x9cflash memoryxe2x80x9d hereinafter) and for semiconductor disk devices which use the flash memory.
FIG. 1 shows an example of the conventional semiconductor disk device. This semiconductor disk device 99 is made up of a disk controller 1 and one or more chips of flash memory 3. The controller 1 includes a host interface logic circuit 14, a flash control interface logic circuit 17, I/O buffers 15 and 16, an MPU 12, an MPU interface logic circuit 13, and a data transfer logic circuit 11, and it implements data writing to the flash memory 3 in response to a write request and for data transferred from the host 2 which is a workstation, personal computer, or the like.
FIG. 2 shows an example of the arrangement of the flash memory 3. This example shows the arrangement including eight flash memory chips indicated by 31 through 38. The flash memory chips have individual lines 521 through 528 of chip select signals wired from the controller 1 (the chip select signal lines 521-528 are shown generically as a wiring 52 at the controller 1 and the interconnection is not shown). Another wiring 51 represents a data bus, address bus and various control signal lines, and it is a common wiring to all flash memory chips. In other words, the data-pin, the address pin and the control signal lines other than the wiring 52 are had in common in the eight flash memory chips, and for example, a signal line A0 in the address bus is connected with each terminal A0 of the eight flash memory chips.
In this arrangement, the controller 1 controls each flash memory chip by selecting a chip in accordance with the chip select signal and issuing a command and address for data to be written.
FIG. 3 shows the write operation of the conventional semiconductor disk device which is arranged as shown in FIG. 2. Shown by the flowchart is the case of sequential and cyclic data writing to the flash memory chips 31-38.
Each block STSn (n=31,32, . . . ,38) is the operation of the controller 1 to check the operational state of a flash memory chip n, and it branches to the direction of Ready if the chip has Ready status or to the direction of Busy if the chip has Busy status. Each block DTn (n=31,32, . . . ,38) is the operation of the host 2 to issue a write command to a flash memory chip n and issue a command of initiating the automatic write operation within the chip for data to be written which is held by the data buffer. Following the operation of DTn, the flash memory chip n writes the data to memory cells based on the in-chip automatic write operation, and it stays in Busy status until the end of writing.
The foregoing arrangement and operation enable the transfer of data and the issuance of write command to the next flash memory chip during the automatic write operation within the former chip, and accomplish the speed-up of data writing based on the parallel writing to multiple flash memory chips.
Recently, there has been devised an efficient flash memory access method based on the early execution of write operation for a flash memory chip which is early detected to be Ready, as illustrated by FIG. 10 of Japanese Patent Unexamined Publication No. H10-63442.
This patent publication No. H10-63442 shown by FIG. 10 is a semiconductor disk having 16 flash memory chips, and for one pattern of the write operation, it can proceeds to the write operation for any flash memory chip which becomes Ready among three flash memory chips having a high, medium and low write-in priority levels.
However, there is given the description of the problem occurring when the write operation is performed with the aforementioned configuration.
There is considered the case in which as shown in FIG. 4, a flash memory chip indicated by chip No. 1 (hereinafter, called chip 1) is a high write-in priority chip, chip 2 is a medium write-in priority chip and chip 3 is a low write-in priority chip, and when chips No. 8 and No. 13 are in Ready status and other chips than the chips No. 8 and No. 13 are in Busy status, the write operation is performed according to the flow chart as in FIG. 10 of the patent publication No. H10-63442. Although the chip in which the write operation is performed is checked its execution ability at the steps S19, S21 and S23 as in the FIG. 10, the decision of the execution ability is performed only for a high priority chip (chip 1) in the step S19, for a medium priority chip (chip 2) in the step S21 and for a low priority chip (chip 3) in the step S23, and despite the existence of chips (chips No. 8 and No. 13) being in Ready status where the write operation is available, the decision that the write operation is unavailable is made and while the write operation is not performed, the next step S25 is proceeded.
In other words, in the conventional configuration, even if there exists one or more flash memory chips being in Ready status after the write operation is done earlier, there raises the problem in which the next write operation can not be performed immediately.
Recently, there has been introduced in Symp. on VLSI Circuits Tech. Digest, 1996, pp. 174-175, a flash memory having multiple banks (will be called xe2x80x9cmulti-bank flash memoryxe2x80x9d) as a scheme of increasing the number of bits of simultaneous writing on a flash memory chip. However, the multi-bank flash memory chip has Busy status during the writing of data to memory cells of one bank, while other banks are left inaccessible. Therefore, this flash memory is problematic in that individual banks cannot be controlled separately from the outside.
The present invention is intended to deal with the foregoing situation, and its prime object is to provide a semiconductor disk device which has a plurality of flash memory chips or one or more multi-bank flash memory chips and is capable of writing immediately to a bank of flash memory chip or multi-bank flash memory chip which has become Ready, and provide a non-volatile semiconductor memory device having a multi-bank flash memory capable of having its banks controlled separately from the outside.
These and other objects and novel features of the present invention will become apparent from the following description of specification taken in conjunction with the accompanying drawings.
In the present invention disclosed in this specification, or other objects and novel features are summarized as follows.
The inventive device has a plurality of banks, allows each bank to operate independently to write data from its data register to memory cells, and is capable of transferring write data from the outside to the data register of each bank even during the write operation of other bank from the data register to memory cells.
The inventive device has a bank selection register which release a signal for designating one of the banks in accordance with the bank status which is established by an external input signal.
The device has a plurality of input terminals of bank enable signals and produces an internal control signal which designates one of the banks based on the combination of the bank enable signals. Data to be written from the outside is transferred to the data register of the designated bank. The device can indicate the status of the designated bank in response to the external status check command. The external read command, erase command, write command and status polling command act on a designated bank.
The inventive device incorporates one or more non-volatile semiconductor memory devices and makes access to said non-volatile semiconductor memory devices in response to disk access requests from a host, wherein the non-volatile semiconductor memory devices have a total number (Nb) of banks of two or more, and a controller device which is connected to the non-volatile semiconductor memory devices and adapted to control the non-volatile semiconductor memory devices has a data buffer with a storage capacity which is greater than the total storage capacity (A) of data registers included in the non-volatile semiconductor memory devices and a buffer control table which temporarily stores the correspondence between the data held by the data buffer and the non-volatile semiconductor memory devices to which the data is to be written.
The data buffer has a storage capacity of 2A or more. The data buffer can be addressed for its divided areas of at least Nb in number. The buffer control table stores for each area of data buffer an identifier indicative of the destination bank of the data to be written which is held in the buffer area, and the device initiates the data writing to the non-volatile semiconductor memory devices, while transferring data from a buffer area, which is relevant to a destination which has become Ready, to the destination.
Information stored for each area of the buffer control table contains priority levels of the transfer of data from the area to the non-volatile semiconductor memory device. Information stored for each area of data buffer includes information which indicates as to whether data held in the area has already been transferred to the non-volatile semiconductor memory device. The buffer control table stores, for each bank of the non-volatile semiconductor memory device, information for addressing an data buffer area, and the addressed area holds data to be transferred to the bank, so that data from a bank which has become Ready is transferred and written to the non-volatile semiconductor memory device. Information of each bank stored in the buffer control table includes address information of multiple data buffer areas indicative of the order of transfer to the bank